Qualifications

This event is open to currently enrolled undergraduate college students at any level and any location in North America, whose expected graduation is not before Spring semester 2012.   

Disciplines/Skills Recommended

• Electrical, Computer Science and Computer System engineering


• Electronics and Manufacturing disciplines.


• Familiarity with Digital Logic Design, Xilinx ISE software and FPGAs

Event Description

This is a virtual event.  Student teams will have approximately two months to create a working digital design to the criteria announced at the event kickoff.  The design effort may require that you:

• Develop block diagrams of the design


• Determine a timing control scheme, create timing diagrams


• Develop state diagrams and truth tables


• Perform mathematical analysis


• Create schematics


• Write code in VHDL or Verilog


• Create design constraints files


• Perform logic simulation and timing analysis

A documentation package must be submitted with the design.  Quality and thoroughness of the design documentation, which demonstrates the disciplined synthesis of ideas and design methodology, is heavily weighted in the judging criteria. 

Schedule

April 14 -- All submissions are due to Avnet by 12pm PST

April 27 -- Winners are announced

Hardware Requirements

To be announced at kick-off.

Grading Summary

30 pts – Creativity and implementation

30 pts – Design process

40 pts – Design documentation

Prizes

Each member (up to 4) of the winning team will receive a scholarship.