1 Team per College

NOTE:  This event is limited to students who are currently taking their first introduction to DIgital Design course, or took the course in the previous semester. 

Disciplines / Skills Recommended

• Electrical, Computer Science and Computer System Engineering, Electronics and Manufacturing disciplines
• Familiarity with Digital Logic Design, Xilinx ISE Software and an FPGA Development Board

Event Description

Students will have 4 hours to create, validate, and document an FPGA design that works on the provided circuitboard.  This may require that you:

• Develop a block diagram of the design
• Determine a timing control algorithm, create time diagrams
• Develop state diagrams and truth tabels
• Perform mathematical analysis
• Create schematics
• Write code in VHDL or Verilog
• Create design constraints files
• Perfom logic simulation and timing analysis
  
  

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The following is an example design challenge (from ATG2009)

Your task :  You are to design a 60-second clock which displays the current time in seconds on a two-digit seven-segment display.  Your clock should operate as follows:

• Upon reset (RESET pushbutton) the clock should display "00" and begin counting
• The clock shall run continuously, changing on one second intervals unless manually paused or reset.
• The count shall be displayed in decimal format.
• While a finger is hold on the PUSH_A button, the clock shall pause with its current value, and then continue counting with the next value when the finger is removed.

Additional considerations:

• You may use any of the board's clock sources so long as the displayed clock counts in one second intervals.  You will be asked to demonstrate the accuracy of your clock.
• You may implement your design with VHDL, Verilog or schematics.  There will be no penalty for the methodology used.
• You will demonstrate and give a 20-minute presentation on your design.
• At the official deadline, you must turn in your presentation and FPGA programming file on a USB memory stick, which will be returned to you at the time of your presentation.  The presentation room will have an identical laptop and set of hardware.

Schedule

Event kick off - 8:00am (Please arrive 30 minutes prior for registration)
Complete the design challenge - 8:00am - 12:00pm
On-the-go-lunch - 11:30am - 1:00pm
Event complete; All projects are due at 12:00pm SHARP
Pre-judging if necessary - 12:00pm - 12:30pm
Judging (time slots will be randomly assigned to all teams) - 12:30pm - 3:00pm
Networking - 3:00pm - 4:00pm
Awards - 4:00pm - 5:00pm

Equipment Requirements

• Avnet will provide laptops preloaded with Xilinx ISE software and PowerPoint. 
• Avnet will provide FPGA developement boards with documentation and additional hardware and IP as needed for the design.
• Avnet will provide a USB memory stick for each team to turn in their design and presentation.
• No other student resources are required or allowed.

Grading Summary (100 pts total)

25 pts - Demonstration of a working design
25 pts - Design process: synthesis of ideas, problem breakdown, design methods
25 pts - Implementation: accuracy and efficiency of actual design, readability
25 pts - Team presentation